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[VHDL-FPGA-Verilog] SPI_controller

Description: SPI serial flash ROM的verilog源代码, 针对winbond W25x16,已经经过逻辑验证,并实际用在芯片设计中,作为一个模块,正常工作.-SPI serial flash ROM in verilog source code for winbond W25x16, logic has been verified, and actually used in chip design, as a module to work.
Platform: | Size: 8192 | Author: Jerd Hu | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: 基于FPGA的SOPC的学习教程，本人找了N久才找到的，希望能帮助到有需要的朋友-SOPC FPGA-based learning tutorial, I looked for a long time to find N, and intend to help a friend in need
Platform: | Size: 468992 | Author: Andy Lao | Hits:

[VHDL-FPGA-Verilog] LCD12864

Description: 利用FPGA编程实现在LCD上显示汉字，非常实用的教程，里面有详细的代码说明，修改后即可实现你的需求。-Using FPGA Programming in LCD display Chinese characters, a very useful tutorial, which has a detailed code instructions can be modified to meet your needs.
Platform: | Size: 337920 | Author: 赵琳 | Hits:

[Crack Hack] 64R4SDFpoint_FFT

Description: 该工程实现了一个64点FFT，verilog编写，采用R4SDF结构，通过Modelsim功能仿真，压缩包里有rtl代码，dc脚本，输出报告。-The project implements a 64-point FFT, verilog compiled by R4SDF structure, through the Modelsim functional simulation, compression bag with rtl code, dc script, the output report.
Platform: | Size: 1255424 | Author: ShuChen | Hits:

[VHDL-FPGA-Verilog] 64pointFFTR2MDC

Description: 该工程实现了一个64点DIF FFT，verilog编写，采用R2MDC结构，通过Modelsim功能仿真，压缩包里有rtl代码，dc脚本，输出报告。-The project implements a 64-point DIF FFT, verilog compiled by R2MDC structure, through the Modelsim functional simulation, compression bag with rtl code, dc script, the output report.
Platform: | Size: 672768 | Author: ShuChen | Hits:

[Software Engineering] FPGAdeguangshanjiancejishu

Description: 本文档设计了1光栅位移传感器信号的接收、光栅位移传感器信号的整形及电平转换电路设计，用Verilog HDL描述了锁相倍频细分和零位信号处理电路。利用FPGA实现光栅位移系统与上位机接口的电路原理框图-This document designed a grating displacement sensor signal reception, grating displacement sensor signal shaping and level conversion circuit design, using Verilog HDL description of segments and zero phase-locked harmonic signal processing circuit. Grating displacement system using FPGA and host computer interface circuit block diagram
Platform: | Size: 1329152 | Author: 于小微 | Hits:

[Documents] Verilog_shuzisheji

Description: 本章的目的是想通过对数字信号处理、计算（Computing）、算法和数据结构、编程语言和 程序、体系结构和硬线逻辑等基本概念的介绍，了解算法与硬线逻辑之间的关系从而引入 利用Verilog HDL 硬件描述语言设计复杂的数字逻辑系统的概念和方法。向读者展示一种 九十年代才真正开始在美国等先进的工业国家逐步推广的数字逻辑系统的设计方法-Purpose of this chapter is to through digital signal processing, computing (Computing), algorithms and data structures, programming languages and programs, the logical architecture and hard-line description of the basic concepts to understand the algorithm and the relationship between hard-line logical to introduce using hardware description language Verilog HDL design complex digital logic concepts and methods. Nineties to show the reader a kind of really started in the United States and other advanced industrial countries to gradually extend the number of logic system design
Platform: | Size: 22794240 | Author: 王双 | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: 这是Verilog HDL硬件描述语言的很好的学习资料，很值得学习！-This is a Verilog HDL hardware description language, a good learning materials, it is worth learning!
Platform: | Size: 4208640 | Author: 杨光 | Hits:

[VHDL-FPGA-Verilog] compare

Description: 一个用verilog写的基本的比较器，其中带了一些其他的电路，也是用verilog编的，希望对读者有用。-Use verilog to write a basic comparator, which brought a number of other circuits, but also with the verilog code, and I hope useful to readers.
Platform: | Size: 125952 | Author: lixu | Hits:

[Other] verilog_RAM

Description: verilog 实现的一个双口RAM及其控制模块.我通过先存入64个数据在读出仿真通过。-verilog implementation of a dual-port RAM.
Platform: | Size: 1024 | Author: 世海 | Hits:

[VHDL-FPGA-Verilog] eda

Description: 利用ATMEL公司的QUETUSii软件编写的verilog语言程序，实现一个带复位、调整时间功能的电子钟，以数码管显示时间，调整时间时调整位闪烁-ATMEL Corporation QUETUSii using software written in verilog language program, the realization of a zone reset, adjust the time function of the electronic clock to digital display of time, adjusting time to adjust bit flash
Platform: | Size: 1591296 | Author: 秦玉龙 | Hits:

[VHDL-FPGA-Verilog] IIC

Description: 用标准Verilog HDL 语言编写的IIC总线IP核，详细定义了时序及输入输出， 可以直接应用-Standard Verilog HDL language of the IIC bus IP core, a detailed definition of the timing and the input and output, can be applied directly
Platform: | Size: 3072 | Author: 吴梁辛 | Hits:

[VHDL-FPGA-Verilog] Focusing-system

Description: 应用FPGA以及VHDL编程语言、视频输入芯片SAA7111和输出芯片SAA7120实现对某固定图像的自动调焦-Application of FPGA and VHDL programming language, video input and output chip SAA7120 SAA7111 chip implementation of a fixed image of the auto-focus
Platform: | Size: 1366016 | Author: 武夷道人 | Hits:

[Program doc] UART_spec

Description: a UART model with FIFO buffer, design with verilog
Platform: | Size: 145408 | Author: quang | Hits:

[VHDL-FPGA-Verilog] Floating-Point-Adder

Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
Platform: | Size: 154624 | Author: 凌音 | Hits:

[VHDL-FPGA-Verilog] PWM

Description: 一个用Verilog实现PWM硬件的开发实例 -PWM hardware using Verilog implementation of a development instance
Platform: | Size: 23552 | Author: lsh | Hits:

[VHDL-FPGA-Verilog] Verilogexample

Description: verilog example 1.NAND Latch To Be Simulated.2.A 16-Bit Counter.3.A D-Type Edge-Triggered Flip Flop.4.A Clock For the Counter.5.The Top-Level Module of the Counter.6.The Counter Module Described With Behavioral Statements.7.Top Level of the Fibonacci Number Generator.8.A NAND Latch.9.The Seed-Number Generator-verilog example 1.NAND Latch To Be Simulated.2.A 16-Bit Counter.3.A D-Type Edge-Triggered Flip Flop.4.A Clock For the Counter.5.The Top-Level Module of the Counter.6 . The Counter Module Described With Behavioral Statements.7.Top Level of the Fibonacci Number Generator.8.A NAND Latch.9.The Seed-Number Generator ....
Platform: | Size: 30720 | Author: vkiy | Hits:

[Other] Verilog-HDL

Description: Verilog-HDL实践与应用系统设计，Verilog-HDL语言是类似于C语言的一种硬件开发语言。-Practice and Application of Verilog-HDL design, Verilog-HDL language is similar to the C language, a hardware development language.
Platform: | Size: 15431680 | Author: 陈俊直 | Hits:

[VHDL-FPGA-Verilog] HDLImplementationoftheVariableStepSize

Description: proposes a Verilog implementation of the Normalized Least Mean Square (NLMS) adaptive algorithm, having a variable step size. The envisaged application is the identification of an unknown system. First the convergence of derived LMS algorithms was analyzed in a Simulink application.
Platform: | Size: 223232 | Author: 陳柏宇 | Hits:

[VHDL-FPGA-Verilog] code

Description: 这是一个数字跑表的代码，用FPGA实现的，对大家或许有用-This is a digital stopwatch in the code, FPGA implementation, perhaps all of us
Platform: | Size: 161792 | Author: 马秀成 | Hits:
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